1. Field of the Invention
The present invention relates to a lock detector and a delay-locked loop having the same, and more particularly to a lock detector and a delay-locked loop having the same for detecting a stable lock state by using analog charging and discharging operations based on a plurality of delay signals.
2. Description of the Related Art
A delay-locked loop (DLL) is a device for generating an internal clock signal that is locked to an external clock signal received from an external source.
The DLL may be a single phase or multiphase clock generator similar to a phase-locked loop (PLL), and is widely used in areas such as communication or control systems in which clock recovery, frequency synthesis, signal modulation, signal demodulation, and so on, are required.
For example, the DLL is frequently used in a cache memory device, which is typically implemented with a static random-access memory (SRAM) for improving data processing speeds between a central processing unit (CPU) and a dynamic random-access memory (DRAM). In addition, the DLL is frequently used in various kinds of logic circuits, synchronous DRAM (SDRAM), Rambus DRAM, etc.
The DLL includes, in general, a delay block for delaying a reference signal and a control block for controlling the delay block such that an output signal of the delay block is locked to the reference signal by comparing the reference signal (i.e., an input signal) with the feedback signal (i.e., the output signal).
In an initial operation time of the DLL, the reference signal and the feedback signal are not synchronized, that is, the DLL is in an unstable state. The feedback signal (i.e., the output signal) is stably locked to the reference signal after a predetermined time. This state is referred to as a lock state, which means that the output signal is stabilized with respect to the input signal.
When the lock state of the DLL is incorrectly determined, the reliability of the DLL and a device using an output of the DLL may be decreased. Therefore, it is important to determine exactly whether or not the DLL is in the lock state.
As a result, a lock detector for determining the lock state of the DLL is required to enhance the reliability of the DLL and other related devices.
A conventional lock detector uses a digital logic type lock detector similar to a lock detector of the PLL, which is described in Korean Patent Laid-Open Publication Nos. 2003-27507 and 2005-41730.
The digital lock detector includes a plurality of logic components such as an AND gate, a NAND gate and so on, in order to form a digital logic for detecting the lock state of the DLL. However, the digital logic may be influenced by variations in environmental conditions such as process, voltage, and temperature (PVT). Thus the logic components included in the DLL may generate noise that causes a malfunction of the DLL.
For example, although an output signal has not been fully stabilized, the digital lock detector may determine that the output signal is locked. In addition, the digital lock detector may not determine whether or not the DLL is in the lock state when a state of the output signal varies due to an abnormal input signal. Therefore, the above problems degrade the reliability of the DLL that requires an accurate operation.
In addition, use of many logic components may increase size of the DLL, thereby degrading an integration degree of an entire chip that includes the DLL and increasing an amount of power for driving the circuit.